1. Field of Invention
The techniques described herein relate to the integration of CMOS circuitry (e.g., formed in silicon) with non-silicon materials and devices.
2. Discussion of the Related Art
The digital revolution has been driven by Moore's Law, that mixed technical and economic law in which there is a net power-law driving force which approximately doubles the transistor density in silicon integrated circuits over approximately a 18-24 month time period. The fuel for this trend has been a mixture of increased technical performance, lower cost, and increased market application as the transistor density has increased. The trend started in the 1960's, but is maturing today. One reason the trend is maturing is power limits prevent easily reducing the size of transistors. Another reason is that increasing the density of standard devices, i.e., PMOSFETs and NMOSFETs, does not create as many new market applications and segments as previously accomplished in the heart of the Moore's Law paradigm years ago.
It has been anticipated for approximately three decades that eventually new materials would be incorporated into silicon CMOS circuits. The inventor has previous experience in the beginning of bringing such innovation to the marketplace, which initiated with the introduction of strained silicon into digital MOS circuits. However, such innovation was accomplished with the insertion of a new element into mainstream silicon CMOS manufacturing: Ge. The time, cost, and return on intimately integrating a new material into current advanced CMOS production facilities is a major limitation for introducing new, monolithically formed materials and devices into silicon CMOS circuits.
In a previous invention by the present inventor, a special engineered substrate was constructed that could be inserted into the beginning of the silicon CMOS process. This substrate contained a buried template layer that could withstand the temperature of a modified CMOS process. After the front-end high temperature steps for the CMOS process are completed, the template can be exposed and III-V device epitaxy can be initiated, then processed, and finished with the CMOS back-end processing, thus producing a monolithic circuit.